| 摘要 |
PCT No. PCT/FI95/00501 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Sep. 14, 1995 PCT Pub. No. WO96/08771 PCT Pub. Date Mar. 21, 1996A method and a circuit arrangement for implementing timing between a microprocessor and its peripheral devices. An address bus and a data bus connect the microprocessor to the peripheral devices to transfer data from the microprocessor to a selected peripheral device, corresponding to writing to the peripheral device, and from a selected peripheral device to the microprocessor, corresponding to reading from the peripheral device. The method comprises generating to the peripheral devices (a) a signal controlling reading (Output Enable), which enables a peripheral device to apply data to the data bus, and (b) a signal controlling writing (Write Enable), which enables data to be written from the data bus to a peripheral device. In order to simplify the equipment and circuit design, at least the signal (GWE) controlling writing is generated by means of an address decoder from the address currently valid on the address bus in such a manner that the moments of the rising and/or falling edges of the signal are dependent on the value of the address and at the same time independent, within the addressing cycle relating to the peripheral device, of the timing determined by the microprocessor, whereby the assertion period of the signal can be adjusted by means of the value of the address. |
