发明名称 |
DIGITAL ARITHMETIC CIRCUIT |
摘要 |
A digital arithmetic circuit (10) includes an inverting circuit (28) connected to a digital circuit (48) in which errors are to be detected. An operand input to the circuit (10) produces an output result in a first operation which is stored in a comparison circuit (82). The operand is inverted by the inverting circuit (28) on a second cycle of operation of the circuit (10) and the output result is compared by the comparison circuit (82) with that from the first operation. A non-zero result from the comparison indicates the occurrence of an error or errors in the operation of the circuit (10).
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申请公布号 |
CA2200715(A1) |
申请公布日期 |
1996.03.28 |
申请号 |
CA19952200715 |
申请日期 |
1995.09.11 |
申请人 |
SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERNMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND NORTHERN IRELAND (THE) |
发明人 |
EVANS, RICHARD ANTHONY |
分类号 |
G06F7/499;G06F7/00;G06F7/506;G06F7/544;G06F11/14;G06F11/16;G06F11/18;(IPC1-7):G06F11/14 |
主分类号 |
G06F7/499 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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