COMPLIANT INTERFACE FOR A SEMICONDUCTOR CHIP

摘要

A method and an apparatus for providing a planar and compliant interface between a semiconductor chip (120) and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads (110) defining channels (117) between adjacent pads. The pads are typically compressed between a flexible film chip carrier (100) and the chip. A compliant filler (170) is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.