发明名称 System and method for generating a template for functional logic symbols
摘要 The system and method improves Electronic Design Automation practices by creating a data template representing pins, elements, and dependencies for numerous components in the same functional class. A pin having the same function is represented once on the data template even if the pin name is different. Sequences of component pins having the same function are combined and are represented by a single pin on the data template. The performance of functional logic symbol generation systems increases significantly because the data template enables the creation of functional logic symbols to be accomplished quickly, accurately, and consistently.
申请公布号 AU3546895(A) 申请公布日期 1996.03.27
申请号 AU19950035468 申请日期 1995.09.08
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 ERIC J VAN DYKE
分类号 G06F17/50 主分类号 G06F17/50
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