发明名称 Method of fabrication of a vertical integrated circuit structure
摘要 The method involves preparing a first substrate (1) with one or more layers (5) with circuit structures and at least one metallised plane (6) near a first main surface. A mask film (8) for subsequent etching of dielectric films is applied to the side of the main surface. Through holes (10) are opened through the mask and first circuit structure layers. The first substrate is connected to an auxiliary substrate (12) on the side of the first main surface. The first substrate is thinned on the side opposite the first main surface. A second substrate (130 is prepared with second main surface, circuit structure layer (15) and metallised plane (16). The substrates are connected by bringing together their sides opposite their main surfaces with some adjustment. The auxiliary substrate is removed. The through holes are opened as far as the second metallised plane using the first substrate's mask as an etching mask. A conducting connection between the metallised planes is formed via the through holes.
申请公布号 EP0703623(A1) 申请公布日期 1996.03.27
申请号 EP19950113414 申请日期 1995.08.26
申请人 FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. 发明人 RAMM, PETER, DR.;BUCHNER, REINHOLD, DIPL.-PHYS.
分类号 H01L21/283;H01L21/302;H01L21/3065;H01L21/768;H01L21/822;H01L27/00;H01L27/06 主分类号 H01L21/283
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