发明名称 INTERRUPTION CONTROL METHOD
摘要 <p>PURPOSE: To provide 89 interruption control method which can surely process an interruption request. CONSTITUTION: When two CPUs 1 and 2 share a DPRAM 3 to perform the mutual communication, one of both CPUs that performs an interruption, reads out a flag which is written in a status area of the DPRAM 3. Then, a flag is written in the status area when the flag has a prescribed logical level, and a code that is written in an interruption area of the DPRAM 3, is read out. A code showing an interruption factor is written in the interruption area when the read code is equal to a prescribed one, and an interruption is applied to the other CPU. The CPU that received the interruption, reads the code out of the interruption area. Then, the flag is read out of the status area and the interruption processing is selected when the flag has a prescribed logical level. The flag of the status area corresponding to the selected processing is cleared at a prescribed logical level and the selected processing is carried out, and the code of the interruption area corresponding to the selected processing is cleared by a prescribed code.</p>
申请公布号 JPH0883190(A) 申请公布日期 1996.03.26
申请号 JP19940217266 申请日期 1994.09.12
申请人 FUJITSU LTD 发明人 SHIIKI HIDEOMI;NAKADA EMI
分类号 G06F15/167;G06F9/46;G06F15/163;(IPC1-7):G06F9/46 主分类号 G06F15/167
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