| 摘要 |
PURPOSE: To obtain a semiconductor device, and fabrication method therefor, in which the occupation area is decreased without sacrifice of an advantage of a trench capacitor cell, i.e., the planarity, using a planar channel type transistor for which fabrication and channel structure can be controlled easily. CONSTITUTION: A capacitor electrode, i.e., an n-type diffusion layer 3, is connected while being self-aligned with the capacitor diffusion layer of a memory cell transistor over the entire periphery of an element region on a p-type Si substrate 1. Since the entire periphery of element region is used as the capacitor electrode, the n-type diffusion layer 3 is pulled down by the HTO side wall except the capacitor side diffusion layer of the memory cell transistor. A capacitor insulation film 4, a plate electrode 5 and an interlayer oxide film 8 are embedded in a trench around the element region. The n-type diffusion layer 3 does not reach the bottom of the trench and a p<+> diffusion layer 6 is formed at a lower part for the purpose of isolation between capacitors. |
