| 摘要 |
PURPOSE: To realize high integration of semiconductor memory on which a lining wiring is formed while enhancing the reliability by substantially planarizing the surface of an upper layer metal wiring for lining a lower layer wiring including the lining part raised on the upper surface of a raised pattern. CONSTITUTION: Word line lining parts 29a, 29b, 19c,... are raised, by means of poly-Si raised patterns 31A, 31B, 31C,..., substantially in flush with conductive patterns 23A, 23B, 23C,..., having a significant level difference from a memory. Consequently, the plane of a tungsten wiring 34 for lining a word line extending over the upper part of trapezoidal patterns 23A, 23B, 23C,... and a gap part 24 along the word line 29 is substantially planarized and only the level difference of second contact holes 32A, 32B, 32C,... as low as 0.3μm is formed on the plane of lining wiring. This structure enhances the resolution at the time of patterning the tungsten wiring 34. |
