| 摘要 |
A frequency synthesizer is disclosed which has a PLL (Phase Locked Loop) made up of voltage controlled oscillator (VCO), variable frequency divider, phase comparator, charge pump, and loop filter. A reference signal source feeds a reference signal to the phase comparator and comprises a reference signal oscillator and a fixed frequency divider. A first and a second waveform converting circuit each divides respective comparison outputs of the phase comparator to produce a charge control signal voltage and a discharge control signal voltage meant for the charge pump. The division of the output periods of the comparison outputs successfully reduces spurious components which are apart from the center frequency of the synthesizer by integral multiples (inclusive of 1) of the reference frequency.
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