| 摘要 |
PROBLEM TO BE SOLVED: To provide a jitter control method for a highly flexible PLL which causes nearly zero feedback delays, is hardly immune to substrate noise nor power supply noise, and can operate at a wide range of frequencies. SOLUTION: The PLL incorporates a phase/frequency detector 10 which uses a dividing circuit and feedback from a clock distributing tree to generate increment and decrement pulses having no 'dead zone'. A jitter is generated when the frequency of a reference clock circuit fluctuates. In a phase locking state, large quantities of currents are gated by charge pumps 14 and 16 in response to the increment and decrement pulses and, in a locked state, small quantities of currents are gated by the pumps 14 and 16. Since the quantities of the currents are reduced, the occurrence of jitters is reduced when the PLL is in the locked state. |
