| 摘要 |
PURPOSE: To provide the phase variable circuit in which resolution of phase difference setting is enhanced without decreasing a period of a clock signal fed to an A/D converter and a variable shift register. CONSTITUTION: This circuit is provided with a frequency divider 10 applying frequency division to a reference clock 9 to provide an output of a clock signal 5, an A/D converter 2 converting an electric signal 1 into digital data 6a synchronously with the clock signal 5, a variable shift register 3 receiving a shift quantity 7 to vary a phase of the digital data 6a and to output digital data 6b whose phase is shifted based on the shift quantity 7 synchronously with the clock signal 5, a counter 11 counting the reference clock 9, outputting an output control signal 3 when the count reaches a set count of 12 resetting the counted value based on the clock signal 5, and a waveform generator 4 converting and outputting the digital data 6b into an analog signal 8 in a timing of the output timing control signal 13. |
