发明名称 |
ARCHITETTURA DI MEMORIA PER DISCHI A STATO SOLIDO |
摘要 |
A solid state disc (SSD) Memory comprising the following functional blocks: a memory block (DATA ARRAY) wherein check data bytes are written; a transcoder memory block (SCRAMBLE RAM) which contains the table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code (ECC) block for implementing the error correction algorithm; an input buffer block (LOGICAL ROW ADDRESS BUFFER) for storing the row addresses coming from the external bus; a non-volatile memory block, programmed during the test stage and available to a possible processor for handling the contents of the transcoder memory (SCRAMBLE RAM); a word counter block (WORD COUNTER) that is driven from the external clock signal (clock) and counts the number of the addressed words and generates the word addresses; two input and output buffer blocks (DATA IN/OUT) for the data to be written in or read out; a multiplexer block (MUX) by which the data stream is driven to the data memory (DATA ARRAY) or to the transcoder memory (SCRAMBLE RAM). <IMAGE> |
申请公布号 |
ITRM940602(A1) |
申请公布日期 |
1996.03.22 |
申请号 |
IT1994RM00602 |
申请日期 |
1994.09.21 |
申请人 |
TEXAS INSTRUMENTS ITALIA S.P.A. |
发明人 |
DI ZENZO MAURIZIO;GRIMANI RODOLFO |
分类号 |
G06F;G06F11/10;G11B20/18;G11C29/00;G11C29/04 |
主分类号 |
G06F |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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