摘要 |
In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods. |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US |
发明人 |
BLAKE, ROBERT MARTIN, WAPPINGERS FALLS, NEW YORK 12590, US;BOSSEN, DOUGLAS CRAIG, POUGHKEEPSIE, NEW YORK 12603, US;CHEN, CHIN-LONG, WAPPINGERS FALLS, NEW YORK 12590, US;FIFIELD, JOHN ATKINSON, UNDERHILL, VERMONT 05489, US;KALTER, HOWARD LEO, COLCHESTER, VERMONT 05446, US |