发明名称 CRC/EDC CHECKER SYSTEM
摘要 EDC/CRC checker (70) performs an EDC/CRC check as a block of data is being corrected during a correction pass, thereby obviating buffer access for EDC/CRC purposes subsequent to block correction. During the correction pass, an EDC/CRC sum is accumulated which, upon completion of the pass of the block, is zero EDC/CRC bytes in the block confirm that the block has been corrected. During the single correction pass of the block, bytes of an uncorrected, most-recent codeword are added to the accumulated sum. Bytes of a previous codeword which have a byte synchronization relationship with the byte of the most-recent codeword are corrected (if necessary), and (when correction occurs) error pattern factors including error patterns used to correct the bytes of the previous codeword are also added to the accumulated sum. In the illustrated embodiment, the block is conceptualized as having columns of codewords and the byte synchronization relationship is such that when an uncorrected byte is being accumulated, correction occurs for a corresponding byte of a next previous codeword. Various embodiments of the invention are capable of handling a plurality of codewords simultaneously.
申请公布号 WO9608874(A1) 申请公布日期 1996.03.21
申请号 WO1995US11988 申请日期 1995.09.15
申请人 CIRRUS LOGIC, INC. 发明人 ZOOK, CHRISTOPHER, P.
分类号 H03M13/00;H03M13/01;H03M13/09;H03M13/33 主分类号 H03M13/00
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