发明名称 |
FLASH EPROM INTEGRATED CIRCUIT ARCHITECTURE |
摘要 |
Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell (75-1, 75-n, 76-1, 76-n) is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and two N columns of flash EPROM cells. M word lines (WL1-WLN), each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines (83, 84) are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array.
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申请公布号 |
WO9608821(A1) |
申请公布日期 |
1996.03.21 |
申请号 |
WO1994US10331 |
申请日期 |
1994.09.13 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD.;NKK CORPORATION;YIU, TOM, DANG-HSING;SHONE, FUCHIA;LIN, TIEN-LER;WAN, RAY, L. |
发明人 |
YIU, TOM, DANG-HSING;SHONE, FUCHIA;LIN, TIEN-LER;WAN, RAY, L. |
分类号 |
G11C17/00;G08G1/017;G11C8/12;G11C16/02;G11C16/04;G11C16/10;G11C16/16;G11C17/12;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C7/00;G11C11/34 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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