发明名称 |
Method for identifying untestable faults in logic circuits |
摘要 |
<p>A method of identifying untestable faults in a logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be untestable if the selected circuit lead were unable to assume a logic 0 and which faults would be untestable if the selected circuit lead were unable to assume a logic 1. Faults that would be untestable in both (hypothetical) cases are identified as untestable faults. Faults which would be untestable if the selected lead were unable to assume a given value may be determined based on an implication procedure. Untestable faults may be identified in a sequential circuit by generating an equivalent combinational iterative array circuit model for a fixed number of time frames. Faults that would be untestable in both (hypothetical) cases and which are located in the last (i.e., latest-in-time) time frame are identified as untestable faults. <IMAGE></p> |
申请公布号 |
EP0702304(A2) |
申请公布日期 |
1996.03.20 |
申请号 |
EP19950306208 |
申请日期 |
1995.09.06 |
申请人 |
AT&T CORP. |
发明人 |
AMBRAMOVICI, MIRON;IYER, MAHESH ANANTHARAMAN |
分类号 |
G01R31/317;G01R31/3183;G01R31/3185;G06F11/22;G06F17/50;(IPC1-7):G06F11/27 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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