Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache

摘要

A data processing system comprised of a memory, a translation lookaside buffer (TLB) providing access to the memory, and an instruction cache connected to the memory. A two entry translation write buffer (TWB) has a first entry that is a first logical register and an associated first physical address register and a second entry that is a second logical register and an associated second physical address register. A physical address bus is connected to the TWB and a logical address bus is connected to the TLB and to the TWB, the logical address bus presenting an instruction pointer to the TLB and to the TWB. The instruction pointer is comprised of logical address bits including upper order bits, lower order bits, and a single bit having a first value or a second value. The single bit provides for translation of even-number pages for which the single bit has the first value and for odd-number pages for which the single bit has the second value. The upper order bits of the logical address are compared with the stored address values in the first and second logical registers in the TWB resulting in a first hit signal with respect to the first logical register or a second hit signal with respect to the second logical register. The first logical register is selected if the single bit has the first value and the second logical register is selected if the single bit has the second value. The physical address bus is driven with the corresponding first or second physical address associated with a selected first or second logical register upon a condition that the upper order bits of the logical address equal a stored value in the first or second logical register in the TWB.