| 摘要 |
A decoder to decode input data which includes an instruction code. The decoder includes a high-order address generator which uses the instruction code in the generation of the high-order address, and a storage circuit which stores control codes that corresponded to the instruction code. Indication data is stored in the beginning or end of the storage area to indicate the number of control codes present in the storage area. The address generated by the high-order address generator locates the desired control codes. A low-order address generator uses the indication data to count the number of control codes and derive a low-order address offset from the high order address. An internal address generator generates an internal address from a combination of the high-order and low-order addresses. The internal address is supplied to the storage circuit serially read out the control codes as the internal address is continuously incremented. The decoded input data is used in the generation of a pattern and to control an electron beam which exposes a wafer.
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