发明名称 Microprocessor system for inhibiting access to memory by checking specific address and specific codes
摘要 A technique for preventing unauthorized operations in a microprocessor system provided for inhibiting access to a memory by checking specific addresses and codes, includes storing main programs and predetermined specific codes in a first memory, the execution of the specific codes by a user being prohibited; storing user programs in a second memory; respectively writing and reading the main and user programs to and from the first and second memories with a CPU; receiving address information over an address bus into a first check circuit, connected between the CPU and the first and second memories; activating a first check signal in the first check circuit to inhibit access to the first memory when an access instruction to a predetermined prohibited address is supplied by the CPU; receiving data information including instruction codes over a data bus into a second check circuit, connected between the CPU and the first and second memories; activating a second check signal in the second check circuit when instruction codes of the user program are the specific codes; receiving the first and second check signals into an inhibit circuit; and inhibiting access to the first and second memories according to the first and second check signals.
申请公布号 US5500949(A) 申请公布日期 1996.03.19
申请号 US19940237416 申请日期 1994.05.03
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAITO, YASUO
分类号 G06F1/00;G06F11/36;G06F12/14;G06F21/00;G06F21/22;G06F21/24;G06K19/073;G06K19/10;(IPC1-7):G06F12/00 主分类号 G06F1/00
代理机构 代理人
主权项
地址