| 摘要 |
<p>A fully pipelined VLSI image processing structure comprising a DCT module (24) for transforming input video signals to produce DCT output signals, an entropy processing module (26) for receiving the DCT output signals and processing them to produce compressed image data signals, and a timing control means (28) for providing timing control signals at predetermined timing interval to control the processing of the input, and the processing of the data signals across the DCT and entropy encoder modules. The DCT output signals are directly transmitted from the DCT module to the entropy encoder module.</p> |
