Schnell einrastender Phasenregelkreis

摘要

A phase lock loop circuit has its bandwidth changed by means of a control signal Cntrl provided by a circuit D monitoring the loop lock state. The monitoring circuit D comprises comparators OP1, OP2 for comparing a parameter related to the phase detector output pulse width with a reference window. In the setting state of the loop, the control signal provided by the monitoring circuit switches the loop filter to a broad bandwidth. When the detector output pulse width corresponds to the window and remains in it for a certain time, the control signal switches the filter to a narrow bandwidth. The control signal changes both the resistance and capacitance values of the filter. Transients caused by switching in the filter is eliminated by precharging of capacitor c3 before switching. The monitoring circuit may include, instead of the comparators OP1, OP2, a pair of counters receiving the phase detector output pulse in anti-phase and clocked by a reference signal. <IMAGE>