Zero phase start optimization using mean squared error in a PRML recording channel

摘要

A "zero phase start" optimization circuit (500) for a Partial Response, Maximum Likelihood ("PRML") data channel determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer (501), a summing junction (502), means (504) for obtaining either an absolute value or squaring function, and an integrator (508). A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.