| 摘要 |
A parallel to serial converter for converting n (n being an integer) bit parallel data streams into a serial data stream including first latch means responsive to a first timing pulse for latching the n bit parallel data streams to produce first n bit parallel data streams, m (m being an integer) second latch means responsive to m second timing pulses for latching the n bit parallel data streams to produce m sets of second n bit parallel data streams, third latch means responsive to the first timing pulse for latching the m sets of second n bit parallel data streams to produce m sets of third n bit parallel data streams, shift register means coupled to the first and third latch means and responsive to the first n bit parallel data streams and the m sets of third n bit parallel data streams and a load pulse for registering (m+1) x n bit data from the first n and m sets of third n parallel data streams and for shifting the (m+1) x n bit data in response to a shift pulse and timing generating means for generating the first timing pulse, m second timing pulses, the load pulse, and the shift pulse, the first timing pulse having one-((m+1) x n)th of the clock rate of the shift clock pulse, each of the m second timing pulses being delayed by one-mth of a period of the first timing pulse, and the load pulse being timed with the first timing pulse. |
