发明名称 |
Bias circuit for a memory line decoder driver of nonvolatile memories |
摘要 |
A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.
|
申请公布号 |
US5499217(A) |
申请公布日期 |
1996.03.12 |
申请号 |
US19940348461 |
申请日期 |
1994.12.02 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L. |
发明人 |
PASCUCCI, LUIGI;GOLLA, CARLA M.;MACCARRONE, MARCO |
分类号 |
G11C17/00;G11C8/10;G11C16/06;(IPC1-7):G11C8/00 |
主分类号 |
G11C17/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|