| 摘要 |
Sub data buses extending in the bit-line direction and sense amplifiers are connected to each other by inside-cell-array-block inside-column-block column select lines which are controlled by (i) column-block select lines extending in the bit-line direction and (ii) inside-cell-array-block column select lines which cross at right angles thereto. The number of the sub data bus pairs is equal to the number of columns which are simultaneously selected by all inside-cell-array-block column select line. According to the present invention, the number of the sub data bus pairs is increased as compared with a conventional DRAM. However, the sub data bus pairs to be connected to the sense amplifiers are limited only to those in a column block selected out of a plurality of column blocks into which cell array blocks are divided. This prevents the power consumption from being increased. Further, column switch transistors connected to each sub data bus are reduced in number to lower the parasitic capacitance, thus enabling a high density DRAM to be operated at a high speed.
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