| 摘要 |
An embodiment of the present invention is a digital circuit (block 12 of FIG. 1) for interfacing between a first bus (10), which can operate synchronously or asynchronously, and a second bus (14), which can operate synchronously or asynchronously, the digital circuit comprising: compelled data decoders (40 and 50) connected to the first bus for receiving compelled data and decoding the compelled data; packet data decoders (52 and 45) connected to the first bus for receiving packet data and decoding the packet data; a digital storage device (28), preferably a FIFO comprising a plurality of write banks and a plurality of read banks or a FIFO comprising a plurality of dual-ported RAMs, having an input selectively connected to the compelled data decoders, the packet data decoders, and the second bus (via lines 44) for storing the decoded data and data from the second bus, the digital storage device additionally includes an output connected to the second bus (via lines 42) for outputting the stored decoded data to the second bus; compelled data encoders connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus; and packet data encoders (34 and 36) connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus. Preferably, multiple bits of data are progressively written into each write bank of the digital storage device within a clock cycle whereby the data is stored at a rate higher than the FIFO could store with a single bank. The first bus can operate synchronously or asynchronously and the second bus can also operate synchronously or asynchronously. The first and second buses can operate at different clock rates and have different data widths.
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