发明名称 Protection circuit
摘要 Independently of a punch-through MOS transistor Q3 used as an I/O protection element in which the drain is connected to an input node or output node and the source is connected to a GND or Vcc, an element for-setting the gate of punch-through MOS transistor Q3 to the GND potential is provided so that its operating speed may be slower than the punch-through speed of the punch-through MOS transistor Q3. In consequence, a high surge applied from I/O terminal can be punched through before the gate insulating film of the punch-through transistor Q3 undergoes a high electric field, to thereby protect the gate insulating film.
申请公布号 US5499152(A) 申请公布日期 1996.03.12
申请号 US19950453810 申请日期 1995.05.30
申请人 NEC CORPORATION 发明人 TAMAKOSHI, AKIRA
分类号 G11C11/413;H02H9/04;(IPC1-7):H02H3/20 主分类号 G11C11/413
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