| 摘要 |
PURPOSE: To provide a DRAM of memory cell structure which is equipped with a trench capacitor and a stacked capacitor, lessened in number of manufacturing processes, and capable of restraining a stacked capacitor ground layer from increasing in height. CONSTITUTION: Memory cells each composed of a MOS transistor and a capacitor are arranged in a matrix for the formation of a DRAM. A trench capacitor is connected to one out of a first MOS transistor and a second MOS transistor adjacent to each other, and a stacked capacitor is connected to the other, the storage electrode 6 of a trench capacitor is formed inside a trench as buried through the intermediary of a capacitor insulating film 5 and connected to the diffusion layer 9 of the first MOS transistor by a connection electrode 10, the storage electrode 17 of the stacked capacitor is formed above the primary surface of a substrate 1 and connected to the diffusion layer 9 of the second MOS transistor, and the storage electrode 17 and the connection electrode 10 are formed of the same layer. |
