| 摘要 |
PROBLEM TO BE SOLVED: To reduce parasitic leakages at an memory array provided with a structure of merged isolation and node trench construction by selectively forming a isolation implant layer near the isolation trench on a deep trench sidewall. SOLUTION: During manufacturing of a memory structure, a deep trench is formed in a silicon substrate by etching, then a sacrificial oxide 64 is grown on the bottom surface and wall surface of the trench. On the wall surface of the trench, a dopant specie is selectively implanted, at a narrow angle, into the silicon substrate through the sacrificial oxide 64, so that a isolation implant layer 70 is formed on the end wall of the trench. Thereby, the occurrence of parasitic leakage is suppressed, and adverse affects on the electric charges accumulated in a deep trench capacitor is avoided. |
