发明名称 ETCHING METHOD,AND FORMATION OF FEATURE,IN HIGH DENSITY INEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To form a circuit element feature smaller than a size which can be manufactured with a specific lithographic exposure tool by conformally, an alternate layer of plural materials of different etch rates within an aperture, further selectively and preferentially etching the material in the alternate layer to form a mask. SOLUTION: At a bit line 30, an insulating cap 34, and a part of a sidewall 36, a polysilicon block or a plug 38 is formed. Then, a thick insulating layer 40 is formed, the insulation layer 40 is flattened to form an aperture 42, which is relatively wide, as far as the surface of the polysilicon block 38. Then, plural layers 44 and 46 of a given material is stuck conformally in succession and flattened at the surface of a TEOS oxide layer 40. The TEOS oxide is etched anisotropically, to form a groove reflecting a polysilicon mask. Meanwhile, about half of the oxide is removed by anisotropic etching as far as almost the surface level of the polysilicon plug 38, so that a deep groove 58 is formed at the polysilicon plug 38.
申请公布号 JPH0864784(A) 申请公布日期 1996.03.08
申请号 JP19950183715 申请日期 1995.07.20
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 BOMII EEBURU CHIEN;GEIRII BERA BURONAA;SON BUAN GUEN
分类号 H01L27/04;H01L21/02;H01L21/306;H01L21/822;H01L21/8242;H01L27/108 主分类号 H01L27/04
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