发明名称 POWER DEVICE INTEGRATED STRUCTURE
摘要 PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gainsαn andαp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting inαn +αp <1, so that thyristor switching is avoided.
申请公布号 JPH0864811(A) 申请公布日期 1996.03.08
申请号 JP19950193264 申请日期 1995.07.28
申请人 SGS THOMSON MICROELETTRONICA SPA;CONSORZIO PERU LA RIC SUULA MAIKUROERETSUTORONIKA NERU METSUTSUOJIORUNO 发明人 JIYUZETSUPE FUERURA;FUERUTSUCHIO FURISHINA
分类号 H01L29/78;H01L29/739;(IPC1-7):H01L29/78 主分类号 H01L29/78
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