发明名称 DISCRIMINATION/TEST DEVICE FOR DEFECTIVE RELIEVING ADDRESS OF SEMICONDUCTOR MEMORY
摘要 PURPOSE: To decide whether relief can be performed or not and a relief address at the same time when a memory is tested. CONSTITUTION: For example, in a memory having two spare cell lines in the directions of row and column, combination in which a defective cell line can be relieved by a spare cell line is made K=(2+2)/(2!.2!)=6 kinds (HT1-6). All six kinds are constituted using each two row discriminating circuits C, column discriminating circuits R for each kind. The row discriminating circuits takes in a row address CA of a defective cell and the column discriminating circuits R take in a column address RA of a defective cell. When a defective cell is detected, four row/column discriminating circuits C, R of each kind take in successively defective row/column addresses from the preceding stage independently for each kind, but do not take the same address. When any of several kinds of discriminating circuits cannot take in a new defective address, also when a new defective address occurs, discrimination output for impossibility of relief HT1-6 are outputted from the kind. Information of each kind is all taken in a CPU 14.
申请公布号 JPH0863998(A) 申请公布日期 1996.03.08
申请号 JP19940196485 申请日期 1994.08.22
申请人 ASIA ELECTRON INC 发明人 SHIBANO KAZUHIRO
分类号 G01R31/28;G06F11/22;G11C11/401;G11C29/00;G11C29/44;H01L21/66 主分类号 G01R31/28
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