| 摘要 |
PURPOSE: To obtain the parallel to serial conversion circuit in which an occupied time of a bus is short when consecutive data are subject to parallel to serial conversion. CONSTITUTION: An initial value of consecutive data being an arithmetic progression is set to a transmission data register 3 and a common difference of the data is stored in a mode register 8 and a final value of the data is stored in an end value register 9. The transmission data register 3 gives its content to a transmission shift register 5 and an adder circuit 11. The transmission shift register 5 applies parallel to serial conversion to the received data. The adder circuit 11 adds a content of the mode register 8 to a content of the transmission data register 3 and gives the sum result to the transmission data register 3 to update the content. A comparator circuit 13 compares the updated content of the transmission data register 3 with a content of the end value register 9 and when they are dissident, the updated content of the transmission data register 3 is given to the transmission shift register 5, in which the data are subject to parallel to serial conversion and when they are coincident, the parallel to serial conversion is terminated. |
