| 摘要 |
<p>A digital electronic system architecture (10) having one more system components (14) and a memory array (12) coupled to selected system components, the memory array selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus (16), coupled to each of the selected system components and to the memory array, for communicating command and control signals among the components and the memory array. The memory array has a plurality of ports (18), each of the ports (i) having an input terminal (32) and an output terminal (34) that transfer data independently of one another, (ii) operating independently of one another (iii) being coupled respectively to one of the other system components for data communication therewith. Read and write interfaces (30, 26) for the memory array are also provided which have queues (64, 52) for receiving data read from a row of the memory array and data to be written to the memory array, respectively. The interfaces also have selection circuits (62, 54) for placing in the queues a contiguous block of read data and in the memory array a contiguous block of received data, respectively. The size of the block and its placement are being selectable.</p> |
