| 摘要 |
PURPOSE:To clearly show the availability segment of a buffer memory, and to improve the availability efficiency of the buffer memory, by providing a flag which displays the classification of control information possible to be stored in an entry corresponding to each entry of the buffer memory. CONSTITUTION:An input/output processor 20 is provided with a transfer circuit 30, a buffer memory circuit 50, and a flag circuit 60. The circuit 30 reads the decodes a transfer program stored in a main memory 10, and selects the input/ output device from which data transfer is started according to a decoded result. Furthermore, the circuit 30 retrieves whether the control information corresponding to the input/output device exists in the memory 50. When it exists, the entry number in the memory 50 in which the control information is stored, is found, and it is set at a register 90 through a bus 301, and a selector 80. The control information to be stored in the memory 50 is read out setting the content of a register 90 as an address, and it is supplied to the circuit 30 through a bus 501. The circuit 30 executes the transfer of the data between the main memory 10 and the input/output device by using the control information. |
