发明名称 Voltage multiplier with linear stabilized output voltage
摘要 <p>An output voltage stabilisation circuit for a voltage multiplier of the type comprising a first charge transfer capacitor (C1) designed to take and transfer electrical charges from the input terminal (IN) to the output terminal (OUT) of a second capacitor (C2) for charge storage connected between the output terminal (OUT) and ground comprises an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage (Vrif) and the output voltage (Vout) of the voltage multiplier and said continuous voltage is applied to one terminal of said charge transfer capacitor (C1). &lt;MATH&gt;</p>
申请公布号 EP0700146(A1) 申请公布日期 1996.03.06
申请号 EP19940830413 申请日期 1994.08.31
申请人 STMICROELECTRONICS S.R.L. 发明人 NICOLLINI, GERMANO;CONFALONIERI, PIERANGELO
分类号 H01L27/04;H01L21/822;H02M3/07;(IPC1-7):H02M3/00 主分类号 H01L27/04
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