| 摘要 |
The memory cell structure (110) is formed in a p-type semiconductor substrate portion (112) which is isolated by field oxide regions (114), and has an n- buried channel/junction region (116), an n+-type drain region (118), and a source structure (120) embedded into it. The source includes a p-type implant and diffusion region (122) with a n+-type region (124) formed within it. The substrate is surfaced by a tunnel oxide (126) or uniform thickness, on which is situated a polysilicon floating gate (128), an inter-gate dielectric (130) and a control gate (132) which define a stacked gate structure (134), formed over the buried channel/junction region and extending between the drain and source regions. |
