发明名称 |
MANAGING HIGH SPEED SLOW ACCESS CHANNEL TO SLOW SPEED CYCLIC SYSTEM DATA TRANSFERS |
摘要 |
A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever a copy of the track contents and in cache and the DASD reaches either an index mark with or a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor operations are enabled.
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申请公布号 |
CA2046709(C) |
申请公布日期 |
1996.03.05 |
申请号 |
CA19912046709 |
申请日期 |
1991.07.10 |
申请人 |
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发明人 |
BEARDSLEY, BRENT CAMERON;BENHASE, MICHAEL THOMAS;CANDELARIA, SUSAN KAY |
分类号 |
G06F3/06;G06F12/08;(IPC1-7):G06F13/14 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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