发明名称 Flip-flop circuit having low standby power for driving synchronous dynamic random access memory
摘要 A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) including a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch. The invention utilizes lower standby power in comparison to prior art flip-flop circuits.
申请公布号 US5497115(A) 申请公布日期 1996.03.05
申请号 US19940235647 申请日期 1994.04.29
申请人 MOSAID TECHNOLOGIES INCORPORATED 发明人 MILLAR, BRUCE;FOSS, RICHARD C.;WOJCICKI, TOMASZ
分类号 G11C11/409;G11C7/10;G11C11/407;G11C11/4096;(IPC1-7):H03K3/356 主分类号 G11C11/409
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