发明名称 |
VITERBI DECODER USING D.S.P PROCESSOR |
摘要 |
a branch matrix operation means for outputting a branch matrix; an addition-comparison-selection means for receiving the branch matrix from the branch matrix operation means and performing an addition-comparison-selection process to output a path matrix and a path determining bit; a path matrix renewal means for searching a state vector having a minimum path matrix by a path matrix renewed in a path time outputted from the addition-comparison-selection means; and a chain back means for receiving a path removing bit and the state vector having the minimum path matrix from the path matrix renewal means, for receiving the path determining bit from the addition-comparison-selection means, for arranging a virtual information bit row to output the arranged bit row to the path matrix renewal means in a path control bit manner or obtain a decoding bit to thereby output the decoding bit to the outside.
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申请公布号 |
KR960003095(B1) |
申请公布日期 |
1996.03.04 |
申请号 |
KR19930026891 |
申请日期 |
1993.12.08 |
申请人 |
KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
KANG, BUP - JOO;MOON, JAE - KYUNG |
分类号 |
H03M13/00;(IPC1-7):H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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