| 摘要 |
A multiplier comprises pulse width modulators (35, 37) for modulating input signals into pulse signals whose pulse widths are corresponding to the levels of the input signals and which are synchronous to each other; an oscillator (39) for outputting a pulse signal at a frequency higher than any of those of the pulse signals from the pulse width modulators; a logical gate portion which receives the pulse signals from the pulse width modulators as well as the pulse signal from the oscillator to execute predetermined logical operation on the pulse signals; and a subtracter (69) which calculates, according to the pulse widths of the pulse signals from the pulse width modulators (35, 37), the number of pulses outputted within a predetermined interval forom the oscillator (39) to provide a signal proportional to the product of levels of the input signals. |
