发明名称 |
Assembly method for large scale integrated circuits |
摘要 |
The method involves a lower substrate (7) with connector pads (8,81) and soldering feet (9) which fit into holes in the second substrate (2). The second substrate has a central hole for the LSI chip (1) and internal connections (5) which run along the base of the chip. There are further smaller holes for the solder feet connection, each of which has an inserted lower/upper substrate connection (3). Track patterns are formed on both sides of the upper substrate. Assembly is by inserting the solder feet into the holes and heating. A layer of resin (10) is placed between the substrates and left to harden. |
申请公布号 |
FR2724052(A1) |
申请公布日期 |
1996.03.01 |
申请号 |
FR19950010225 |
申请日期 |
1995.08.30 |
申请人 |
NEC CORPORATION |
发明人 |
TAMURA KOETSU;HASEGAWA SHINICHI |
分类号 |
H01L21/56;H01L23/495;H05K3/30;H05K3/32;H05K3/34;H05K3/36 |
主分类号 |
H01L21/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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