| 摘要 |
<p>A processor which has a plurality of windowed registers. Each of the windowed registers comprise IN, OUT and LOCAL window registers. The IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also has a cache of at least four sets of cache registers with switchable addresses. Each set of cache registers is capable of holding data of the IN, OUT or LOCAL window registers. The addresses of each set of cache registers are changed to the addresses of a different set of cache registers when the current window changes during a save or restore operation.</p> |
