| 摘要 |
<p>Memory circuitry (200) is provided which includes first and second banks of memory cells (201a, 201b) arranged in rows and columns. Row decoder circuitry (210) is included for selecting a row in at least one of the memory banks (201) in response to a row address. Row address circuitry (208, 209, 215) is provided for presenting a sequence of the row addresses to the row decoder circuitry (210) in response to a single row address provided at an address port to memory circuitry (200). Column decoder circuitry (213) is further included for selecting a column in each of the banks (201) in response to a column address. Column address circuitry (211, 212, 215) presents a sequence of the column addresses to the column decoder circuitry (213) in response to a single column address received at the address port to memory circuitry (200).</p> |
