An improved electronic memory and methods for making and using the same

摘要

The memory comprises several multi-bit storage locations (201) in an array of rows and columns with a row decoder coupled to a row line. The multi-bit storage location has a first FET with a source/drain path coupled to a corresponding column line and a gate coupled to a corresponding row line and another FET with a source/drain path coupled in series with the source/drain path of the first transistor and a gate coupled to control signal source local to the storage location. A number of data storage capacitors (211) are coupled to the source/drain path of the corresponding transistors and the control signal source local to the storage location is operable to turn-on the storage to transfer charge between two capacitors while the row decoder maintains the first transistor in a turned-off state. Data can be written into and read out of the cells (209) of a selected location (201) by shifting voltages between the capacitors and the associated column line (204).