发明名称
摘要 PURPOSE:To prevent the generation of disconnection of communication by dividing a consecutive bit string in a PN series for a long period as a scrambler initial value and using the value while being varied for each frame thereby inserting a scrambler to an input data. CONSTITUTION:A PN series generating circuit 2 in a transmission section 1 generates a PN series with a sufficiently longer period than the stage number of a reset scrambler 3. The scrambler 3 fetches a consecutive bit series by the stage number of the scrambler 3 sequentially from the PN series by one frame each and it is used as a scrambler initial value to scramble an input data 11. A PN series synchronizing circuit 6 in a reception section 5 fetches a scrambler initial value from a reception data 13 and reproduces the original PN series by taking synchronization of the PN series to apply bit error protection of the scrambler initial value. A reset descrambler 7 fetches a consecutive bit series by the number of stages of the descrambler 7 from the PN series recovered being an output of the circuit 6 and uses is as a scrambler initial value to descramble the data 13.
申请公布号 JPH0817364(B2) 申请公布日期 1996.02.21
申请号 JP19890261614 申请日期 1989.10.06
申请人 发明人
分类号 H04K1/00;H04K1/02;H04L9/16;H04L9/18;H04L9/22;(IPC1-7):H04K1/02 主分类号 H04K1/00
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