| 摘要 |
PURPOSE: To provide a CMOS input buffer circuit for a DRAM and a microprocessor, etc., insensitive to the fluctuation of a threshold voltage and symmetrical power supply noise. CONSTITUTION: This input buffer is provided with an input stage 12' formed by (p) and (n) channel MOS transistors Q1' and Q2' constituted so as to be provided with practically equal transconductance. The transistors Q1' and Q2' are connected so as to form a serial current path between a bias voltage and a low voltage (ground, for instance) and the trip point of the input stage 12' is set to the almost middle of specified TTL logic high level and low level. A difference between the bias voltage for operating the input buffer and the low voltage is secured so as to turn off at least one of the MOS transistors Q1' and Q2' for TTL logic high or low level input and to evade power consumption while input signals are at such a level. Also, the input buffer is insensitive to the symmetrical power supply noise, hardly consumes power and is also insensitive to the fluctuation of the threshold voltage. |
