发明名称 BIT PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To instantaneously establish synchronism by two phase clocks by extracting a data signal and a data signal slightly delayed from the original data signal by a positive phase clock, detecting whether a changed point of the data signal matches the edge of the positive phase clock or not and extracting the data signal by the positive phase clock or a reverse phase clock in accordance with the detected result. CONSTITUTION:A data signal D0 inputted from an input data signal terminal 1 is inputted to a delay circuit 3 and a DFF circuit 4. An input data signal D1 passing through the circuit 3 is inputted to a DFF circuit 5. These DFF circuits 4, 5 enter the data by a positive phase clock CK inputted from a clock input terminal 2 and detect whether a changed point of the data matches the edge of the positive phase clock or not. When the changed point does not match the edge of the positive phase clock as the result of detection, the data signal is extracted by the positive phase clock, and when matches the edge, the data signal is extracted by a reverse phase clock.
申请公布号 JPH0851417(A) 申请公布日期 1996.02.20
申请号 JP19940202977 申请日期 1994.08.05
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAWANO RYUSUKE;HIRATA MICHIHIRO
分类号 H03L7/00;H04L7/02;H04L25/40 主分类号 H03L7/00
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