发明名称 |
CMOS process and circuit including zero threshold transistors |
摘要 |
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.
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申请公布号 |
US5493251(A) |
申请公布日期 |
1996.02.20 |
申请号 |
US19940349503 |
申请日期 |
1994.12.02 |
申请人 |
IMP, INC. |
发明人 |
KHAMBATY, MOIZ;PETERSEN, COREY D. |
分类号 |
H01L21/8238;(IPC1-7):H01L25/00 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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