| 摘要 |
A circuit for converting samples of data received at a high sampling rate into data samples at a low sampling rate integrally related to the high sampling rate and with the low rate samples synchronized with the high rate samples without a complex phase control apparatus. A memory stores and transfers data under control of write and read address signals. The read address signals are derived by combining the write address signals with a difference address signal generated by a circuit including a modulo counter with a modulus corresponding to the integral ratio between the high and low sampling rates, a first sample-and-hold circuit for storing the count of the modulo counter and supplying its count to an allocating circuit which generates the difference address signal and supplies same to a combining circuit. A decoder controlled by the modulo counter supplies a clock signal at the low sampling rate to a second sample-and-hold circuit fed with data from the memory. The second sample-and-hold circuit outputs synchronized data at the low sampling rate.
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